? semiconductor components industries, llc, 2015 january, 2015 ? rev. 1 1 publication order number: tcp?3033n/d TCP-3033N 3.3 pf passive tunable integrated circuits (ptic) introduction on semiconductor?s ptics have excellent rf performance and power consumption, making them suitable for any mobile handset or radio application. the fundamental building block of our ptic product line is a tunable material called parascan , based on barium strontium titanate (bst). ptics have the ability to change their capacitance from a supplied bias voltage generated by the control ic. the 3.3 pf ptics are available as wafer-level chip scale packages (wlcsp) and in qfn packages for easy mounting directly on printed circuit boards. key features ? high tuning range and operation up to 20 v ? usable frequency range: from 700 mhz to 2.4 ghz ? high quality factor (q) for low loss ? high power handling capability ? compatible with ptic control ic tcc-103 ? wlcsp package: 0.722 x 1.029 x 0.611 mm (10 pillar) ? qfn package: 1.200 x 1.600 x 0.950 mm ? qfn: msl?2 moisture sensitivity level (per j?std?020) ? these devices are pb?free and rohs compliant typical applications ? multi-band, multi-standard, advanced and simple mobile phones ? tunable antenna matching networks ? tunable rf filters ? active antennas www. onsemi.com functional block diagram marking diagram x.x = 3.3 n = normal tuning ptic bias rf1 rf2 x.xn wlcsp10 1.03x0.72 case 567kd qfn6 1.6x1.2 case 485dx ptic functional block diagram device package shipping ? ordering information tcp?3033n?dt wlcsp10 (pb?free) 4000 units / 7? reel tcp?3033n?qt qfn6 (pb?free) 8000 units / 13? reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d.
tcp?3033n www. onsemi.com 2 typical specifications representative performance data at 25 c table 1. performance data parameter min typ max units operating bias voltage 2.0 20 v capacitance (v bias = 2 v) 2.84 3.30 3.63 pf capacitance (v bias = 20 v) 0.90 0.94 0.99 pf tuning range (2 v - 20 v) 3.00 3.50 4.05 tuning range (20 v - 2 v) 2.80 3.30 4.05 leakage current (wlcsp) 4.0 a operating frequency 700 2400 mhz quality factor @ 700 mhz, 10 v 90 quality factor @ 2.4 ghz, 10 v 60 ip3 (v bias = 2 v) [1,3] 70 dbm ip3 (v bias = 20 v) [1,3] 85 dbm 2nd harmonic (v bias = 2 v) [2,3] -65 dbm 2nd harmonic (v bias = 20 v) [2,3] -75 dbm 3rd harmonic (v bias = 2 v) [2,3] -40 dbm 3rd harmonic (v bias = 20 v) [2,3] -70 dbm transition time (cmin cmax) [4] 80 s transition time (cmax cmin) [4] 70 s 1. f 1 = 850 mhz, f 2 = 860 mhz, pin 25 dbm/tone 2. 850 mhz, pin +34 dbm 3. ip3 and harmonics are measured in the shunt configuration in a 50 environment 4. rf1 and rf2 are both connected to dc ground
tcp?3033n www. onsemi.com 3 representative performance data at 25 c for 3.3 pf wlcsp package figure 1. capacitance figure 2. harmonic power figure 3. ip3 figure 4. q table 2. absolute maximum ratings parameter rating units input power +40 dbm bias voltage +25 (note 5) v operating temperature range ?30 to +85 c storage temperature range ?55 to +125 c esd ? human body model class 1a jedec hbm standard (note 6) stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 5. wlcsp: recommended bias voltage not to exceed 20 v 6. class 1a defined as passing 250 v, but may fail after exposure to 500 v esd pulse
tcp?3033n www. onsemi.com 4 assembly considerations and reflow profile the following assembly considerations should be observed: cleanliness these chips should be handled in a clean environment . electro-static sensitivity on semiconductor?s ptics are esd class 1a sensitive. the proper esd handling procedures should be used. mounting the wlcsp ptic is fabricated for flip chip solder mounting. connectivity to the rf and bias terminations on the ptic die is established through copper pillar posts (53 m nominal height) topped with lead-free sac351 solder caps (28 m nominal height). the ptic die is rohs-compliant and compatible with lead-free soldering profile. post-reflow cleaning use of ultrasonic cleaning is not recommended for pillared devices as it may lead to premature fatigue failure of the pillars. molding the ptic die is compatible for over-molding or under-fill. figure 5. reflow profile orientation of the ptic for optimum losses when configuring the ptic in your specific circuit design, at least one of the rf terminals must be connected to dc ground. if minimum transition times are required, dc ground on both rf terminals is recommended. to minimize losses, the ptic should be oriented such that rf2 is at the lower rf impedance of the two rf nodes. a shunt ptic, for example, should have rf2 connected to rf ground. figure 6. ptic orientation functional block diagram bias rf ant rf1 (ptic pad) rf2 (ptic pad)
tcp?3033n www. onsemi.com 5 part number definition table 3. part numbers part number capacitance package 2 v 20 v tcp?3033n-dt 3.30 0.94 10-pillar wlcsp tcp?3033n-qt 3.30 0.94 6-pin qfn for information on device numbering and ordering codes, please download the device nomenclature technical note (tnd310/d) from www.onsemi.com .
tcp?3033n www. onsemi.com 6 package dimensions wlcsp10, 1.03x0.72 case 567kd issue a seating plane 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max 0.590 millimeters a1 d 1.029 bsc e b1 0.044 0.094 e 0.150 bsc 0.639 e d a b pin a1 reference e4 0.05 c c b a 0.06 c a1 c 0.069 0.093 0.722 bsc dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.05 c 2x top view side view bottom view note 3 e e1 0.114 bsc recommended package outline 12 a1 b 0.079 0.129 a e3 detail a e2 0.300 bsc e3 0.460 bsc e4 0.425 bsc detail a a 0.05 b c 0.03 c 8x b detail b e d e1 e2 8x b1 detail b a 0.05 b c 0.03 c 2x b1 2x b 0.13 2x 0.59 0.57 0.15 2x 0.60 2x 0.48 0.13 2x 0.41
tcp?3033n www. onsemi.com 7 package dimensions qfn6 1.6x1.2, 0.5p case 485dx issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. a seating plane 0.05 c a1 2x 2x 0.05 c dim a min max millimeters 0.90 1.00 a1 0.00 0.05 b 0.22 0.28 d e a3 pin one identifier 0.05 c 0.10 c a 0.10 c e b b 3 6 6x 1 4 0.03 c mounting footprint* 1.60 bsc 1.20 bsc 0.15 ref bottom view l 6x dimensions: millimeters 0.60 6x 0.30 6x 1.40 0.50 pitch *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. l1 ??? 0.15 top view b side view recommended a3 d e package outline 1 c e 0.50 bsc a detail b ??? ??? 0.39 0.46 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 tcp?3033n/d parascan is a trademark of paratek microwave, inc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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